(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to both dual and single inverse copper damascene processes to form conducting copper interconnects and contact vias, simultaneously, with low dielectric constant intermetal dielectrics (IMD).
(2) Description of Related Art
As an introduction and background to Prior Art, the conventional dual damascene process scheme is commonly used to fabricate of copper interconnects, trench, and contact vias. Dual Damascene wiring interconnects (and/or studs) are formed by depositing one or two dielectric layers on a planar surface, patterning it using photolithography and dielectric reactive ion etch (RIE), then filling the recesses with conductive copper metal. The excess metal is removed by chemical mechanical polishing (CMP), while the troughs or channels remain filled with inlaid metal. With the dual damascene process, two layers of metal are formed as one, i.e., wiring line and contact stud vias, avoiding an interface between the layers.
Related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,512,514 entitled "Self-Aligned Via and Contact Interconnect Manufacturing Method" granted Apr. 30, 1996 to Lee shows an inverse interconnect process where the line is patterned and then the intermetal dielectric (IMD) layer is formed there're. Described is an integral via structure and contact manufacturing process with a first conductive layer patterning process section that includes: depositing a first conductive layer , creating a first via etch mask on the first conductive layer, and through a series of process steps, formed is a first conductive pattern having integral via structure. A second conductive layer is patterned in the same manner as the first conductive layer to create a second conductive pattern with integral second via structures. A second dielectric layer is deposited and planarized in the same manner as the first dielectric exposing the second via structures. A third conductive layer is deposited, making contact with the second via structures and patterned with convention methods to create a third conductive pattern.
U.S. Pat. No. 5,981,374 entitled "Sub-Half-Micron Multi-Level Interconnection Structure and Process Thereof" granted Nov. 9, 1999 to Dalal et al. teaches an interconnect process and structure for sub-half-micron multi-level IC interconnects. The structure and process are reported to improve circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.
U.S. Pat. No. 5,693,568 entitled "Reverse Damascene Via Structures" granted Dec. 2, 1997 to Liu et al. shows a reverse dual damascene process. An interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. The need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided.
U.S. Pat. No. 5,705,430 entitled "Dual Damascene with a Sacrificial Via Fill" granted Jan. 6, 1998 to Avanzino et al. describes a dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The openings are filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings, conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment, the sacrificial material is not etch-able by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in the conductive line and via openings.
U.S. Pat. No. 5,691,238 entitled "Subtractive Dual Damascene" granted Nov. 25, 1997 to Avanzino et al. describes a method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.
U.S. Pat. No. 5,795,823 entitled "Self Aligned Via Dual Damascene" granted Aug. 18, 1998 to Avanzino et al. discloses a method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the etchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its etchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.